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产品型号：512MB DDR2 533 (FB DIMM ECC)
生产厂商：Transcend(创见)
产品类型：服务器内存
产品系列：Fully Buffered ECC(FB ECC DDRII533)
关 注 度：11733
价    格：￥立即咨询

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内存容量:512MB , 工作频率:533MHz .

Description

The TS64MFB72V5J-T is a 64M x 72bits DDR2-533 Fully Buffered DIMM. The TS64MFB72V5J-T consists of 9 pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA package, 1 pcs AMB IC, and a 2048 bits serial EEPROM on a 240-pin printed circuit board. The TS64MFB72V5J-T is a 240pin fully buffered dual in-line memory module. The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The Advanced Memory Buffer interface is responsible for handling channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the memory channel. Fully Buffered DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface.

Features

•             240pin fully buffered dual in-line memory module

•             3.2Gb/s, 4.0Gb/s link transfer rate

•             1.8V +/- 0.1V Power Supply for DRAM VDD/VDDQ

•             1.5V +/- 0.075V Power Supply for AMB VCC

•             3.3V +/- 0.3V Power Supply for VDDSPD

•             Buffer    Interface    with     high-speed    differential point-to-point Link at 1.5 volt

•             Channel error detection & reporting

•             Channel fail over mode support

•             Serial presence detect with EEPROM

•             4 Banks

•             Posted CAS

•             Programmable CAS Latency : 3, 4, 5

•             Automatic DDR2 DRAM bus and channel calibration

•             MBIST and IBIST Test functions

A	133.35+0.15	5.250+0.006
B	51	2.0
C	67	2.64
D	5	0.197
E	2.5	0.0980
F	1.5+0.10	0.059+0.039
G	5.175	0.204
H	3.25	0.128
I	3	0.118
J	9.5	0.374
K	18.8	0.74
L	30.35+0.15	1.2+0.006
M	1.27+0.10	0.050+0.004
N	6.80	0.268

SCK	System Clock Input, positive line
/SCK	System Clock Input, negative line
PN[13:0]	Primary Northbound Data, positive lines
/PN[13:0]	Primary Northbound Data, negative lines
PS[9:0]	Primary Southbound Data, positive lines
/PS[9:0]	Primary Southbound Data, negative lines
SN[13:0]	Secondary Northbound Data, positive lines
/SN[13:0]	Secondary Northbound Data, negative lines
SS[9:0]	Secondary Southbound Data, positive lines
/SS[9:0]	Secondary Southbound Data, negative lines
SCL	Serial Presence Detect (SPD) Clock Input
SDA	SPD Data Input / Output
SA[2:0]	SPD Address Input, also used to select the DIMM number in the AMB
VID[1:0]	Voltage ID: these pins must be unconnected for DDR2-base Fully Buffered DIMMs VID[0] is VDD value:OPEN=1.8V,GND=1.5V VID[1] is Vcc value:OPEN=1.5V,GND=1.2V
RESET	AMB reset signal
RFU	Reserved for Future Use
VCC	AMB Core Power and AMB Channel interface Power (1.5 Volt)
VDD	DRAM Power and AMB DRAM I/O Power (1.8 Volt)
VTT	DRAM  Address/Command/Clock  Termination Power (VDD/2)
VDDSPD	SPD Power
VSS	Ground