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产品型号：2GB DDR2 400 (REG ECC)
生产厂商：Transcend(创见)
产品类型：服务器内存
产品系列：Registered ECC Memory(DDRII400)
关 注 度：11248
价    格：￥立即咨询

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Description

The TS256MQR72V4K is a 256M x 72bits DDR2-400 Registered DIMM. The TS256MQR72V4K consists of 36 pcs 128Mx4 bits DDR2 SDRAMs in 60 ball FBGA package, 4 pcs register in 96 ball uBGA package, 1 piece PLL driver IC and a 2048 bits serial EEPROM on a 240-pin printed circuit board. The TS256MQR72V4K is a Dual In-Line Memory Module and is intended for mounting into 240-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features

•          RoHS compliant products.

•          JEDEC standard 1.8V ± 0.1V Power supply

•          VDDQ=1.8V ± 0.1V

•          Max clock Freq: 200MHZ; 400Mb/S/Pin.

•          Posted CAS

•          Programmable CAS Latency: 3,4,5

•          Programmable Additive Latency :0, 1,2,3 and 4

•          Write Latency (WL) = Read Latency (RL)-1

•          Burst Length: 4,8(Interleave/nibble sequential)

•          Programmable sequential / Interleave Burst Mode

•          Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

•          Off-Chip Driver (OCD) Impedance Adjustment

•          MRS cycle with address key programs.

•          On Die Termination

•          Serial presence detect with EEPROM

A	133.35+0.15	5.250+0.006
B	55.00	2.165
C	63.00	2.480000
D	5.00	0.197
E	2.50	0.0980
F	1.50+0.10	0.059+0.039
G	5.175	0.204
H	2.20	0.867
I	4.00	0.157
J	10.00	0.394
K	17.80	0.701
L	30.00+0.15	1.181+0.006
M	1.27+0.10	0.050+0.004

A0~A13, BA0, BA1	Address input, bank address
DQ0~DQ63	Data Input / Output.
CB0~CB7	Data Check Bits Input/Output
DQS0~DQS8	Data strobe
/DQS0~/DQS8	Data strobe , negative line
CK0, /CK0	Clock Input.
CKE0, CKE1	Clock Enable Input.
ODT0, ODT1	On-die termination control line
/CS0, /CS1	Chip Select Input.
/RAS	Row Address Strobe
/CAS	Column Address Strobe
/WE	Write Enable
DM0~DM8	Data-in Mask
/DQS9~/DQS17	Data strobes(Read),negative line
VDD	+1.8 Voltage power supply
VDDQ	+1.8 Voltage Power Supply for DQS
VREF	Power Supply for Reference
VDDSPD	Serial    EEPROM    Positive    Power Supply
SA0~SA2	Address select for EEPROM
SCL	Serial PD Clock
SDA	Serial PD Add/Data input/output
VSS	Ground
/RESET	Register and PLL control pin
/Err_Out	Parity error found in the bus
Par_In	Parity bit for address and control bus
NC	No Connection